1. Field of the Invention
The present invention relates to a DC-DC converter controller, and more particularly relates to a DC-DC converter with constant on-time control.
2. Description of the Prior Art
FIG. 1 is a schematic diagram of a DC-DC converting circuit with low voltage ripple and high frequency hysteretic disclosed in U.S. Pat. No. 6,369,555. The DC-DC converting circuit comprises a buffer circuit 2, a hysteresis comparator 4, a feedback circuit 6 and a driver circuit 8. The feedback circuit 6 is coupled to an output end of the hysteresis comparator 4 and provides a ramp voltage VRAMP to an input end of the buffer circuit 2. The input end of the buffer circuit 2 receives a superimposed signal VREF′ of the ramp voltage VRAMP and a reference voltage VREF (i.e., VREF′=VREF+VRAMP). A non-inverting input end of the hysteresis comparator 4 is coupled to an output end of the buffer circuit 2 and an inverting input end thereof is coupled to an output voltage VOUT, and the output end thereof is coupled to the driver circuit 8. The driver circuit 8 may be a power transistor which is coupled to an input voltage VIN and an LC filter 12. The LC filter 12 supplies the output voltage VOUT.
The amplitude of the ramp voltage VRAMP is related to the amount of the input voltage VIN and the amount of the output voltage VOUT. FIG. 2 is waveforms of the superimposed signals shown in FIG. 1 in the different applications of the input voltage and the output voltage. A signal CLK_ON represents the duty cycle of the driver circuit 8. Both the direct current components of superimposed signals VREF′1 and VREF′2 are the reference voltage VREF, and a valley values and a peak values are determined by the input voltage VIN and the output voltage VOUT. Thus, the different applications cause the different peak values and valley values of the superimposed signals VREF′1 and VREF′2. The hysteresis comparator 4 executes judgment according to the peak value and the valley value of the superimposed signal VREF′. Such circuit characteristics will cause the hysteresis comparator 4 having the different offset voltages in the different applications, as shown in FIG. 2. The amounts of offset voltages Voffset1 and Voffset2 of the superimposed signals VREF′1 and VREF′2 are different to cause feedback signals FB1 and FB2 indicative of the output voltage VOUT being also different. Therefore, such circuit structures make the amount of the output voltage VOUT be different in different applications.